Senior Signal Integrity Engineer (Canada)

About the job

Delart is home to a team of world-class engineers and project leaders dedicated to developing the next generation of advanced networking technologies, consumer devices, and innovative technology solutions. Trusted by some of the world’s leading technology companies, we deliver highly scalable, mission-critical solutions that power both consumer and business applications globally.

Since our founding in 2017, we have been at the forefront of designing cutting-edge networking, telecommunications, and consumer products, while driving end-to-end project execution and creating transformative technology applications.

Overview

Lead the advancement of signal and power integrity solutions for state-of-the-art high-speed digital interfaces, driving robust interface performance through rigorous electromagnetic simulation and in-depth PCB design proficiency. This role is instrumental in developing practical design guidelines and ensuring the reliability of digital links operating up to 448Gbps within advanced hardware systems.

Responsibilities

• Conduct high-frequency electromagnetic simulations of next-generation interfaces (224Gbps, 448Gbps) utilizing tools such as Ansys HFSS and Keysight ADS.
• Execute detailed power delivery network (PDN) analysis with industry-standard simulation software.
• Analyze and validate signal integrity for advanced PAM4 (56Gbps, 112Gbps) and NRZ (minimum 25Gbps) digital interfaces, including comprehensive eye diagram, jitter/noise, and S-parameter correlation between simulation and measurement data.
• Develop, apply, and document best practices in impedance control, transmission line design, PCB stack-ups, and practical PCB manufacturing processes within actionable guidelines.
• Prepare precise technical documentation on simulation approaches, findings, and recommendations to inform and support the hardware development lifecycle.
• Integrate a working knowledge of Ethernet high-speed interface standards (25G/100G/400G/800G) into simulation and analysis tasks.
• Partner with PCB layout engineers to evaluate and optimize board layouts for signal and power integrity in server, data center, and network hardware platforms.

Minimum Qualifications

• Minimum 5 years of direct, hands-on experience performing signal integrity simulations for high-speed digital systems.
• Demonstrated proficiency with Ansys HFSS, Cadence Sigrity, PowerSI, Ansys SIwave, and Keysight ADS.
• Proven expertise with high-speed digital links, including PAM4 (56Gbps, 112Gbps) and NRZ (≥25Gbps).
• Extensive knowledge of signal and power integrity methodologies, PCB stack-up optimization, impedance control, and fabrication/process constraints.
• Strong organizational skills along with exceptional technical documentation capabilities.

Preferred Qualifications

• Master’s degree in Electrical Engineering, Physics, Mathematics, or a related technical discipline, or equivalent professional experience.
• 8+ years of experience with end-to-end signal and power integrity analysis for high-performance electronic hardware.
• Expertise in authoring comprehensive design guidelines for ultra-high-speed interconnects and electronic systems.
• Experience in direct collaboration with PCB fabrication vendors to implement and verify complex impedance-controlled circuit board layouts.