Firmware Memory Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

• At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
• Together, we advance your career.

THE ROLE:

The Memory IO team is looking for a passionate and experienced Firmware designers for the pre/post-silicon development of high-speed LPDDR, DDR and inter-chip IO IPs.  Be a part of the definition, design and development and productization phase of industry-leading Memory PHYs and interface IP.  This opportunity includes enabling of new PHY designs at the microarchitecture, firmware/hardware co-design, and algorithm design level.

Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge Memory interfaces.

THE PERSON:

Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills

RESPONSIBILITIES:

• Firmware design and development of DDR PHY & DRAM Training steps
• Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power
• Pre-silicon FW coding and simulation against Architectural and RTL models
• Post-silicon lab bring-up and optimization of DDR Init and Run Time FW
• Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin
• Working with SoC/Product firmware teams to define features and specs
• PREFERRED EXPERIENCE: Excellent knowledge of C, C++ and any scripting language, such as Python.
• Good Knowledge of Verilog/SystemVerilog and digital simulation debug.
• Ability to adapt learn new toolsets and frameworks is required.
• Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and synchronization is a plus
• Post-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, Memory Controller Design experience is preferred
• Strong understanding of computer organization/architecture.
• Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.
• Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)
• ACADEMIC CREDENTIAL: Bachelor's degree in Electrical or Computer engineering is strongly desired. Master's or PhD degree is a plus.
• LOCATION: Austin, TX  -  Open for Boxborough, MA
• **This role is not eligible for visa sponsorship.

Responsibilities

THE ROLE:

The Memory IO team is looking for a passionate and experienced Firmware designers for the pre/post-silicon development of high-speed LPDDR, DDR and inter-chip IO IPs.  Be a part of the definition, design and development and productization phase of industry-leading Memory PHYs and interface IP.  This opportunity includes enabling of new PHY designs at the microarchitecture, firmware/hardware co-design, and algorithm design level.

Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit and architecture teams develop leading edge Memory interfaces.

THE PERSON:

Will have strong analytical/problem-solving skills and pronounced attention to details. Must be a self-starter, and able to independently drive tasks to completion. Will have strong interpersonal and communication skills

RESPONSIBILITIES:

• Firmware design and development of DDR PHY & DRAM Training steps
• Firmware development of DDR PHY for ATE Testing, IP Char & SoC Power
• Pre-silicon FW coding and simulation against Architectural and RTL models
• Post-silicon lab bring-up and optimization of DDR Init and Run Time FW
• Post-silicon DDR Training enhancements to enable robust links for higher reliability / higher frequency margin
• Working with SoC/Product firmware teams to define features and specs
• PREFERRED EXPERIENCE: Excellent knowledge of C, C++ and any scripting language, such as Python.
• Good Knowledge of Verilog/SystemVerilog and digital simulation debug.
• Ability to adapt learn new toolsets and frameworks is required.
• Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and synchronization is a plus
• Post-silicon experience developing firmware on real hardware is required. Experience with SERDES, DDR, Memory Controller Design experience is preferred
• Strong understanding of computer organization/architecture.
• Laboratory experience, including the use of equipment: oscilloscopes, logic analyzers, etc.
• Experience with low level, physical phenomena-oriented logic design is an asset (dealing with IO, clocking, voltage control, etc.)
• ACADEMIC CREDENTIAL: Bachelor's degree in Electrical or Computer engineering is strongly desired. Master's or PhD degree is a plus.
• LOCATION: Austin, TX  -  Open for Boxborough, MA
• **This role is not eligible for visa sponsorship.

Qualifications