Physical Design Engineer - Block Level, Subsystem Implementation

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference

. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.

Key Responsibilities

• Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.
• Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.
• Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).
• Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level.
• Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.
• Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow.
• Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.
• You may be a good fit if you have
• 5-10+ years of previous experience with PD
• Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
• Experience with back-end design and timing closure on advanced process nodes (5nm and below)
• Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
• Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
• Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
• Scripting ability in Tcl, Python, or Perl for flow automation and debug
• Deeply creative and able to think from first principles
• Strong candidates may also have experience with Familiarity with modern ML and LLM model architectures
• Ability to program with Python or another scripting language
• Familiarity with AI tools for programming/coding
• Startup experience or comfort working in fast-paced environments