Core RTL/Microarchitecture Power Lead

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

Do you want to be at the forefront of designing the next Ryzen or Epyc CPU?  AMD is seeking an experienced and creative processor designer to analyze and drive power efficient microarchitecture development for the Core pipeline in our the next-generation processor. This is a cross-functional role where you will work closely with the RTL, Architecture, Physical Design and Validation teams to evaluate and optimize the power consumption of the design.

You should be highly experienced in the microprocessor development process and have a consistent track record of delivering timely, high-quality products. A broad and thorough understanding of low-power design techniques, microprocessor architecture and RTL logic design is required.

KEY RESPONSIBILITIES:

• Analyze power consumption of new and existing micro-architectural features of Next Generation High-Performance CPU Cores. Propose and drive the development of new features and optimizations for existing logic.
• Analyze power characteristics of the latest Server/Client CPU workloads and use the data to influence microarchitecture decisions.
• Collaborate with the RTL team to improve the implementation. Asist them in interpreting power analysis results from tools such as PTPX. Work with the team to gather correct estimates of dynamic power consumption and savings that can be achieved through design optimizations.
• Collaborate with the Physical Design Team to achieve low power while utilizing the latest cutting-edge fabrication technologies.
• Collaborate with the Design Verification Team to generate tests that activate the functions under study.
• Validate power consumption of features in Silicon. Analyze any discrepancies with pre-Silicon projections and provide feedback to the design process.
• Work with the tools and methodologies teams to define and update tools to aid power analysis. Use AI to develop tools and improve the workflow.
• Deliver high-quality products on schedule while working with engineers that act as one team.
• Required experience: Expert level experience in High-Performance Microprocessor Design.
• Experience must include a strong level of experience in low power design techniques with industry tools in a CPU, GPU or devices of similar complexity.
• Preferred experience: Register Transfer Level (RTL) coding for high-speed designs
• Verilog/System Verilog, RTL Methodology, Coding practices
• Logic design
• Working with Performance simulators, workloads and analyzing their results
• Coding and techniques for Low Power
• Exposure to Verification methods
• Experience with Timing closure, Physical Design, Synthesis, or Place and Route
• Problem Solving and Debugging Skills
• Excellent Communication and Documentation Skills
• Using AI and LLMs to aid development, improve quality and automate workflows.
• Scripting such as Ruby, Python, Perl, or Shell is a plus
• Academic credentials: MS EE/CE/CS plus years of relevant experience preferred
• LOCATION: Santa Clara, Ca
• This role is not eligible for visa sponsorship.

Responsibilities

THE ROLE:

Do you want to be at the forefront of designing the next Ryzen or Epyc CPU?  AMD is seeking an experienced and creative processor designer to analyze and drive power efficient microarchitecture development for the Core pipeline in our the next-generation processor. This is a cross-functional role where you will work closely with the RTL, Architecture, Physical Design and Validation teams to evaluate and optimize the power consumption of the design.

You should be highly experienced in the microprocessor development process and have a consistent track record of delivering timely, high-quality products. A broad and thorough understanding of low-power design techniques, microprocessor architecture and RTL logic design is required.

KEY RESPONSIBILITIES:

• Analyze power consumption of new and existing micro-architectural features of Next Generation High-Performance CPU Cores. Propose and drive the development of new features and optimizations for existing logic.
• Analyze power characteristics of the latest Server/Client CPU workloads and use the data to influence microarchitecture decisions.
• Collaborate with the RTL team to improve the implementation. Asist them in interpreting power analysis results from tools such as PTPX. Work with the team to gather correct estimates of dynamic power consumption and savings that can be achieved through design optimizations.
• Collaborate with the Physical Design Team to achieve low power while utilizing the latest cutting-edge fabrication technologies.
• Collaborate with the Design Verification Team to generate tests that activate the functions under study.
• Validate power consumption of features in Silicon. Analyze any discrepancies with pre-Silicon projections and provide feedback to the design process.
• Work with the tools and methodologies teams to define and update tools to aid power analysis. Use AI to develop tools and improve the workflow.
• Deliver high-quality products on schedule while working with engineers that act as one team.
• Required experience: Expert level experience in High-Performance Microprocessor Design.
• Experience must include a strong level of experience in low power design techniques with industry tools in a CPU, GPU or devices of similar complexity.
• Preferred experience: Register Transfer Level (RTL) coding for high-speed designs
• Verilog/System Verilog, RTL Methodology, Coding practices
• Logic design
• Working with Performance simulators, workloads and analyzing their results
• Coding and techniques for Low Power
• Exposure to Verification methods
• Experience with Timing closure, Physical Design, Synthesis, or Place and Route
• Problem Solving and Debugging Skills
• Excellent Communication and Documentation Skills
• Using AI and LLMs to aid development, improve quality and automate workflows.
• Scripting such as Ruby, Python, Perl, or Shell is a plus
• Academic credentials: MS EE/CE/CS plus years of relevant experience preferred
• LOCATION: Santa Clara, Ca
• This role is not eligible for visa sponsorship.

Qualifications