PLL Design/ Integration Sr Staff Engineer

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THE ROLE:

We are seeking a highly motivated and experienced Staff Design Engineer to join our AECG Fabric team. In this role, you will lead and contribute to the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across cutting-edge process nodes.

As an integral part of AMD's Programmable Logic Group, our global Clock/PLL team is responsible for implementing programmable clocking solutions and methodologies across AMD's expanding portfolio of Adaptive Embedded Computing products. Each new Adaptive SoC introduces a fresh set of programmable clock challenges, driven by evolving system and functional architectures, as well as the adoption of new semiconductor and packaging technologies.

Our team collaborates closely with functional architecture, programmable fabric, integration, and software teams to design and deliver innovative clocking solutions — spanning new architectures, clock IPs, tools, and flows.

This position offers the opportunity to join a team of industry experts, where you will invent and implement original solutions to complex clocking challenges in some of the largest and most sophisticated SoCs in the industry.

THE PERSON:

You bring a solid foundation in IC design and manufacturing, including experience with analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators), chip design, silicon processes, and packaging technologies. A strong understanding of device physics, reliability, and silicon chip manufacturing is essential.

You have a passion for modern adaptive computing architectures and post-silicon validation and characterization. You thrive in collaborative environments, communicate effectively across teams, and bring strong analytical and problem-solving skills to every challenge. You are eager to learn, ready to take initiative, and excited by emerging technologies and innovation.

KEY RESPONSIBILITIES:

• Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider in to FPGA products across cutting-edge process nodes.
• Lead the integration of different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range at product level.
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization for Product level Jitter optimization
• Supervise and verify layouts produced by PD engineers to ensure floor planning, matching, and parasitic minimization using advanced node technologies
• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
• Conduct comprehensive system-level simulations and validation for PLL IP integration in FPGA environment using Vivado or similar tools/flows.
• PREFERRED EXPERIENCE: Experience designing fractional-N PLLs, All-Digital PLLs (ADPLL) and/or sub-sampling PLLs is a plus
• Familiarity with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers
• Background in digital design, digital verification, and SystemVerilog modeling
• Knowledge of clock synthesis and recovery techniques, including PLLs, DLLs, and CDRs
• ACADEMIC CREDENTIALS: Preferably holds an advanced degree (MS) in electrical & electronics engineering; alternatively, a bachelor’s degree with several years of relevant industry experience is acceptable.
• This role is not eligible for visa sponsorship.

Responsibilities

THE ROLE:

We are seeking a highly motivated and experienced Staff Design Engineer to join our AECG Fabric team. In this role, you will lead and contribute to the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across cutting-edge process nodes.

As an integral part of AMD's Programmable Logic Group, our global Clock/PLL team is responsible for implementing programmable clocking solutions and methodologies across AMD's expanding portfolio of Adaptive Embedded Computing products. Each new Adaptive SoC introduces a fresh set of programmable clock challenges, driven by evolving system and functional architectures, as well as the adoption of new semiconductor and packaging technologies.

Our team collaborates closely with functional architecture, programmable fabric, integration, and software teams to design and deliver innovative clocking solutions — spanning new architectures, clock IPs, tools, and flows.

This position offers the opportunity to join a team of industry experts, where you will invent and implement original solutions to complex clocking challenges in some of the largest and most sophisticated SoCs in the industry.

THE PERSON:

You bring a solid foundation in IC design and manufacturing, including experience with analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators), chip design, silicon processes, and packaging technologies. A strong understanding of device physics, reliability, and silicon chip manufacturing is essential.

You have a passion for modern adaptive computing architectures and post-silicon validation and characterization. You thrive in collaborative environments, communicate effectively across teams, and bring strong analytical and problem-solving skills to every challenge. You are eager to learn, ready to take initiative, and excited by emerging technologies and innovation.

KEY RESPONSIBILITIES:

• Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider in to FPGA products across cutting-edge process nodes.
• Lead the integration of different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range at product level.
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization for Product level Jitter optimization
• Supervise and verify layouts produced by PD engineers to ensure floor planning, matching, and parasitic minimization using advanced node technologies
• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
• Conduct comprehensive system-level simulations and validation for PLL IP integration in FPGA environment using Vivado or similar tools/flows.
• PREFERRED EXPERIENCE: Experience designing fractional-N PLLs, All-Digital PLLs (ADPLL) and/or sub-sampling PLLs is a plus
• Familiarity with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers
• Background in digital design, digital verification, and SystemVerilog modeling
• Knowledge of clock synthesis and recovery techniques, including PLLs, DLLs, and CDRs
• ACADEMIC CREDENTIALS: Preferably holds an advanced degree (MS) in electrical & electronics engineering; alternatively, a bachelor’s degree with several years of relevant industry experience is acceptable.
• This role is not eligible for visa sponsorship.

Qualifications