Principal Chipset Project Engineer II

About the job

As the Principal Chipset Project Engineer you will serve as the primary technical leader for the engineering planning and execution of the chipset from early product definition stages through launch. This is a high-stakes, cross-functional leadership role that bridges the gap between hardware architecture, IP development, physical implementation, and software readiness.

Your ultimate goal is to deliver "the most efficient chipset solution for the agentic era" on-schedule, within budget, and at Power, Performance, Area, and Cost (PPA-C) metrics.

In this role, you will drive end-to-end technical execution across a highly matrixed global workforce to ensure custom hardware innovations land seamlessly in production and are optimized for first-party software experiences.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $275000 - $382000 (USD) + 30% bonus target + equity + benefits

Learn more about

benefits at Google.

Responsibilities

• Direct the execution of the entire SoC lifecycle, from initial chip definition and top-level architecture through tape-out, silicon bring-up, and final mass production.
• Collaborate with DSPG Silicon, Software, and Pixel Hardware teams to drive a "one team" model, ensuring hardware innovations have day-one software sponsorship and land seamlessly in production.
• Coordinate deliverables across a highly matrixed global workforce, aligning schedules, managing dependencies, and actively resolving complex technical blockers.
• Lead critical debug forums to drive complex system failure signatures to rapid root-cause closure by driving actions across all teams.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
• 15 years of experience with custom silicon design, SoC/ASIC implementation, or hardware-software co-design.
• 10 years of experience in technical leadership.
• Experience, including experience directing SoC development programs from concept to mass production.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
• Experience managing global, cross-functional engineering deliverables and aligning schedules/dependencies across matrixed organizations.
• Demonstrated change-management and operational leadership skills, with experience coordinating teams across global sites.
• Expertise in driving complex hardware and software system-level debug and root-cause analysis.
• Deep technical understanding of custom IP integration, physical design flows, and hardware-software co-design principles.