Sr Solutions Engineer-FPGA/PCIe

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

Join our team to architect and develop cutting-edge hardware/software co-design solutions for ASIC/FPGA-based acceleration across a wide range of applications—such as networking, storage, automotive, aerospace, and emerging AI/ML workloads. You will design high-performance hardware acceleration engines and embedded software that orchestrates them, enabling next-generation compute platforms.

THE PERSON:

You are passionate about modern processor architecture, digital design, and system-level validation. You thrive in collaborative environments, communicate effectively across global teams, and bring strong analytical and problem-solving skills. You are eager to learn and tackle complex technical challenges.

KEY RESPONSIBILITIES:

• Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for Ips
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be developed
• RTL Development: Design, verify, and validate high-performance logic using System Verilog/Verilog. You will focus on the data and control path, implementing deigns for PCIe (Gen 6/7), CXL, UAL, Ethernet, and DDR5/6.
• System Level Integration: Utilize the standard ASIC flows , AMD (Xilinx) Vivado ecosystems to integrate custom IP with other subsystems
• Pre-Si Verification: Perform pre-silicon verification and emulation to ensure functional correctness and performance
• Post-Si Validation: Lead the "Bring-up" process in the lab. Perform post-silicon validation, debugging complex interactions between the embedded software and hardware fabric
• PREFERRED EXPERIENCE: Hands-on experience with ASIC/FPGAs
• RTL Expertise: Expert in SystemVerilog/Verilog, synchronous design, and timing closure for high-speed logic
• Protocols: Knowledge of PCIe, AXI, DDR, and Ethernet. Familiarity with CXL or UAL is highly desirable
• Verification: Familiarity with UVM-based verification frameworks and emulation platforms (Palladium, Protium, Zebu)
• Validation: Experience in hardware debugging
• Tools: Proficiency in Python, Tcl, Makefiles, and Shell scripting for automation
• ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering
• LOCATION: San Jose CA
• This role is not eligible for visa sponsorship.

Responsibilities

THE ROLE:

Join our team to architect and develop cutting-edge hardware/software co-design solutions for ASIC/FPGA-based acceleration across a wide range of applications—such as networking, storage, automotive, aerospace, and emerging AI/ML workloads. You will design high-performance hardware acceleration engines and embedded software that orchestrates them, enabling next-generation compute platforms.

THE PERSON:

You are passionate about modern processor architecture, digital design, and system-level validation. You thrive in collaborative environments, communicate effectively across global teams, and bring strong analytical and problem-solving skills. You are eager to learn and tackle complex technical challenges.

KEY RESPONSIBILITIES:

• Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for Ips
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be developed
• RTL Development: Design, verify, and validate high-performance logic using System Verilog/Verilog. You will focus on the data and control path, implementing deigns for PCIe (Gen 6/7), CXL, UAL, Ethernet, and DDR5/6.
• System Level Integration: Utilize the standard ASIC flows , AMD (Xilinx) Vivado ecosystems to integrate custom IP with other subsystems
• Pre-Si Verification: Perform pre-silicon verification and emulation to ensure functional correctness and performance
• Post-Si Validation: Lead the "Bring-up" process in the lab. Perform post-silicon validation, debugging complex interactions between the embedded software and hardware fabric
• PREFERRED EXPERIENCE: Hands-on experience with ASIC/FPGAs
• RTL Expertise: Expert in SystemVerilog/Verilog, synchronous design, and timing closure for high-speed logic
• Protocols: Knowledge of PCIe, AXI, DDR, and Ethernet. Familiarity with CXL or UAL is highly desirable
• Verification: Familiarity with UVM-based verification frameworks and emulation platforms (Palladium, Protium, Zebu)
• Validation: Experience in hardware debugging
• Tools: Proficiency in Python, Tcl, Makefiles, and Shell scripting for automation
• ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering
• LOCATION: San Jose CA
• This role is not eligible for visa sponsorship.

Qualifications