Physical Design Engineer

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Description

APPLE INC has the following available in Austin, Texas. ASIC Block level physical design: Working on a design in GPU(Graphics Processing Unit) through all steps of Physical Design, including Floor planning, Placement, Clock Tree Synthesis, Routing, Timing, Physical verification and Electrical Analysis; Floor planning, pin assignment, macro placement, logic placement, Clock Tree Synthesis and routing analysis : steps involved in while working on block, eg.

Placing the memories in design, placing the input output ports, placing the logic in design, creating clock tree which delivers clock to whole logic in design and then do routing of signals between logical cells in design; Low-power techniques including clock gating, power gating, and multi-voltage designs : These are the various techniques used for reducing power consumption in design; Physical verification: DRC and LVS requirements: Also involved in checking design rule checks and layout vs schematic so that the design complies with

fabrication requirements and doesn't result in failures later; Static Timing Analysis including block closure : Also involved in meeting timing requirements so that design can run on specific frequency (how fast the design can work); EMIR Analysis and closure : Also involved in taking care of Electromigration and Electrical Analysis so that design doesn't fail due to excessive current issues later; and Perl, Shell scripting, TCL, Python : Scripting techniques are used to extract data from designs and analyze them.

40 hours/week.

Minimum Qualifications

• Master’s Degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.
• Education and/or experience must include: Using MOS, VLSI Circuit Design, or Computer System with transistor level fundamentals and design architecture for physical design work and troubleshooting.
• Using physical design tools including Innovus or IC Compiler for block level floor planning, place and route.
• Using static timing analysis tools including Primetime for hierarchical design approach, top-down design, budgeting, timing closure.
• Using physical verification tools including Caliber for design rule closure.
• Using tools including Voltus for electrical analysis.
• Using Genus or DC Compiler and Innovus or IC Compiler to work with RTL teams to drive optimal floor planning and physical implementation through early RTL feedback
• Using physical design tools including Innovus or IC Compiler for innovative physical construction and optimization flows to push performance, power, and Area (PPA)
• Using scripting languages including Perl, Tcl, or Python for parsing physical design reports, logs and creating design metrics that capture the state of the design and to configure tool capabilities.

Preferred Qualifications

• N/A