Semiconductor Device Modeling Engineer

Job Details:

Job Description:

About the team and organization

Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies.

As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications. As a semiconductor device modeling engineer, you will be playing a key role to support compact modeling activities for Intel's new technologies.

Qualifications:

• Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Master's degree in Electrical Engineering or a related discipline and at least 5+ years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline with a minimum of 3+ years of industry experience in the semiconductor field.
• 3+ years of hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
• Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc.
• Strong background in IV/CV fitting, model retargeting, and corner/statistical variation modeling.
• Experience developing LLE models for FinFET or GAAFET technologies.
• Skilled in Python scripting for automation and documentation.

Preferred Qualifications

• Ph.D. in Electrical Engineering or a related discipline with 8+ years of industry experience in the semiconductor field.
• Deep expertise in compact modeling, including one or more of the following areas: Layout-dependent effects (LDE) and their impact on circuit performance.
• Modeling using Open Model Interface (OMI)
• Strong understanding of process flow, layout, and basic circuit design/simulation.
• Modeling self-heating effects and their influence on device and circuit performance.
• Development of methodologies for device targeting (e.g., transistors) and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models.
• o    Demonstrated experience in technical leadership and Proven capability to collaborate across multiple teams and geographies.
• Experience with machine learning algorithms and their application is data analysis and compact model development.
• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary Location: US, Oregon, Hillsboro

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A