Power Management Architect - Bangalore

Role Overview

Velaura is designing the compute silicon that powers robots, autonomous systems, and intelligent machines that operate in the physical world—where energy is scarce, thermal headroom is limited, and every milliwatt affects range, runtime, and performance.

As Power Management Architect for our Physical AI System-on-Chip (SoC), you will own the power architecture of our silicon: defining how the chip delivers, distributes, and manages energy across compute, AI/NPU, memory, and I/O so that our platforms hit their performance targets within tight power and thermal budgets.

This is a foundational, cross-cutting role spanning silicon, firmware, platform software, and product teams. You will set Velaura’s power management strategy from the earliest architecture phase through tape-out and production—shaping power delivery, voltage and frequency scaling, low-power states, and the hardware/software control that keeps Physical AI systems efficient in the field.

Responsibilities

• Own the SoC power architecture: define power domains, voltage/frequency (DVFS) strategy, power states, and the power delivery network across Velaura’s Physical AI silicon roadmap.
• Define dynamic and static power management techniques including clock and power gating, adaptive voltage scaling, body biasing, and retention strategies, to maximize performance-per-watt for AI and real-time workloads.
• Establish power and energy budgets and model them across use cases; drive power, performance, and area (PPA) trade-offs with architecture, design, and product teams.
• Architect the on-die power management and control subsystem—PMIC interface, power management controller, sensors, and telemetry—and the firmware/software policies that drive it.
• Partner with silicon design, firmware, thermal, package, and platform software teams to embed power intent (e.g., UPF) into the design flow and validate it through implementation and silicon bring-up.
• Define power and thermal management for sustained real-world operation, including thermal throttling, energy-aware scheduling, and safe operating limits.
• Establish power architecture standards, modeling methodology, and review practices; mentor engineers and raise the power-engineering bar across the organization.
• Required Qualifications
• 8+ years in power management, mixed-signal, or SoC architecture, with significant experience defining power architecture for shipping silicon or embedded platforms.
• Deep expertise in low-power design techniques: multiple power domains, DVFS, clock/power gating, adaptive voltage scaling, retention, and power state management.
• Strong understanding of power delivery networks, PMICs, voltage regulation, and the interaction between power, thermal, and package constraints.
• Hands-on experience with power intent and low-power methodology (e.g., UPF/CPF) and with power modeling and analysis across the SoC design flow.
• Experience working across silicon design, firmware, and platform software to define and validate power management policies from architecture through silicon bring-up.
• Bachelor’s or advanced degree in Electrical/Computer Engineering or a related field, or equivalent practical experience.
• Excellent written and verbal communication skills, with a track record of influencing technical direction and mentoring engineers.

Preferred Qualifications

• Experience optimizing power for AI/ML accelerators or NPUs and for real-time or latency-sensitive edge workloads.
• Familiarity with robotics, automotive, mobile, or other power- and thermally-constrained domains, and with battery and energy-storage considerations.
• Experience with energy-aware software/firmware, thermal management, and silicon power characterization and correlation.
• Prior experience at an early-stage or high-growth semiconductor or hardware company, building power architecture and methodology from the ground up.