RTL Design Engineer

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THE ROLE:

We are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad range of embedded microprocessor (MP) subsystems and hardware accelerators that are critical to enhancing performance, functionality, security, and efficiency across AMD System-on-Chip (SoC) products spanning client, server, graphics, and gaming platforms.

In this role, you will contribute to block-level RTL design and subsystem-level integration for complex embedded MP subsystems. Your work will directly influence technologies including security policy management, cryptography, data compression, high-throughput DMA, power management, and other advanced subsystem applications.

You will collaborate closely with the IP Architecture team to define functional specifications, establish and track design objectives, and drive RTL development through implementation and optimization. Working alongside experienced design engineers, you will help deliver high-quality solutions that meet performance, power, and area (PPA) targets while maintaining robust design quality and scalability.

THE PERSON:

You are a talented and results-oriented RTL design engineer with a strong track record of technical ownership and execution. You are passionate about developing high-quality hardware designs and driving complex IP and subsystem projects from concept through completion.

You proactively identify opportunities to improve methodologies and workflows, anticipate and resolve technical challenges, and thrive in a fast-paced, collaborative environment. You possess strong analytical and problem-solving skills, exceptional attention to detail, and excellent written and verbal communication abilities. You are also committed to supporting team success through collaboration, knowledge sharing, and mentorship.

KEY RESPONSIBILITIES:

• Develop and maintain block-level RTL IP and MP subsystem specifications, microarchitecture, RTL implementations, and associated design methodologies and infrastructure.
• Design, implement, and debug RTL solutions using AI-powered methodologies, directed C-DPI based testing, and verification team testbenches and regression environments, to achieve functional and coverage closure.
• Analyze regression failures, debug simulations, evaluate coverage results, and collaborate with design, verification, and implementation teams to achieve functional and design-quality closure, including lint, timing, DFT, DFP, and other signoff requirements.
• Contribute to verification planning by reviewing feature specifications, defining test plans, influencing testbench architecture, and promoting design-for-verification best practices.
• Debug and resolve subsystem and SoC integration issues in collaboration with SoC Integration, SoC Design Verification, emulation, and post-silicon validation teams.
• Provide technical leadership in IP architecture, RTL design methodologies, and critical problem resolution, commensurate with experience level.
• PREFERRED EXPERIENCE
• Strong understanding of CPU and embedded microprocessor subsystem architectures, datapath-oriented accelerator microarchitectures, and FPGA-based emulation and prototyping methodologies.
• Proficiency in Verilog and SystemVerilog, along with scripting languages such as Python, Tcl, Perl, Ruby, and Make.
• Solid knowledge of both traditional and AI-powered RTL design and verification methodologies, industry best practices, and C-DPI based verification techniques.
• Strong understanding of industry-standard bus and interface protocols, including AXI, AHB, and AMBA.
• Experience with ASIC development tools and flows, including simulation, debug, linting, synthesis, timing analysis, and power-aware verification.
• Domain-specific expertise in security, processor subsystems, accelerators, or related areas, along with demonstrated technical leadership capabilities for senior-level candidates.
• ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• Master's degree preferred.
• Location: Austin, TX ( Open to Markham, ON )
• This role is not eligible for visa sponsorship.

Responsibilities

THE ROLE:

We are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad range of embedded microprocessor (MP) subsystems and hardware accelerators that are critical to enhancing performance, functionality, security, and efficiency across AMD System-on-Chip (SoC) products spanning client, server, graphics, and gaming platforms.

In this role, you will contribute to block-level RTL design and subsystem-level integration for complex embedded MP subsystems. Your work will directly influence technologies including security policy management, cryptography, data compression, high-throughput DMA, power management, and other advanced subsystem applications.

You will collaborate closely with the IP Architecture team to define functional specifications, establish and track design objectives, and drive RTL development through implementation and optimization. Working alongside experienced design engineers, you will help deliver high-quality solutions that meet performance, power, and area (PPA) targets while maintaining robust design quality and scalability.

THE PERSON:

You are a talented and results-oriented RTL design engineer with a strong track record of technical ownership and execution. You are passionate about developing high-quality hardware designs and driving complex IP and subsystem projects from concept through completion.

You proactively identify opportunities to improve methodologies and workflows, anticipate and resolve technical challenges, and thrive in a fast-paced, collaborative environment. You possess strong analytical and problem-solving skills, exceptional attention to detail, and excellent written and verbal communication abilities. You are also committed to supporting team success through collaboration, knowledge sharing, and mentorship.

KEY RESPONSIBILITIES:

• Develop and maintain block-level RTL IP and MP subsystem specifications, microarchitecture, RTL implementations, and associated design methodologies and infrastructure.
• Design, implement, and debug RTL solutions using AI-powered methodologies, directed C-DPI based testing, and verification team testbenches and regression environments, to achieve functional and coverage closure.
• Analyze regression failures, debug simulations, evaluate coverage results, and collaborate with design, verification, and implementation teams to achieve functional and design-quality closure, including lint, timing, DFT, DFP, and other signoff requirements.
• Contribute to verification planning by reviewing feature specifications, defining test plans, influencing testbench architecture, and promoting design-for-verification best practices.
• Debug and resolve subsystem and SoC integration issues in collaboration with SoC Integration, SoC Design Verification, emulation, and post-silicon validation teams.
• Provide technical leadership in IP architecture, RTL design methodologies, and critical problem resolution, commensurate with experience level.
• PREFERRED EXPERIENCE
• Strong understanding of CPU and embedded microprocessor subsystem architectures, datapath-oriented accelerator microarchitectures, and FPGA-based emulation and prototyping methodologies.
• Proficiency in Verilog and SystemVerilog, along with scripting languages such as Python, Tcl, Perl, Ruby, and Make.
• Solid knowledge of both traditional and AI-powered RTL design and verification methodologies, industry best practices, and C-DPI based verification techniques.
• Strong understanding of industry-standard bus and interface protocols, including AXI, AHB, and AMBA.
• Experience with ASIC development tools and flows, including simulation, debug, linting, synthesis, timing analysis, and power-aware verification.
• Domain-specific expertise in security, processor subsystems, accelerators, or related areas, along with demonstrated technical leadership capabilities for senior-level candidates.
• ACADEMIC CREDENTIALS: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• Master's degree preferred.
• Location: Austin, TX ( Open to Markham, ON )
• This role is not eligible for visa sponsorship.

Qualifications