Senior Analog and Mixed Signal Design Engineer

Job Details:

Job Description:

The Group

Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of the analog/mixed-signal and high-speed I/O IP that defines what Intel's leading-edge process technologies can deliver. The High-Speed I/O team develops SerDes and die-to-die interface reference designs and test chips that co-optimize Intel process technology with next-generation wireline standards, including high-speed PAM4 electrical links, PCIe, UCIe, and HBM.

The Role

We are seeking a senior technical expert in high-speed SerDes circuit design and SerDes system architecture. You will own SerDes link architecture on Intel's leading technology test chips, from link budget and equalization strategy down to transistor-level design of the critical analog front-end and clocking blocks. You will also translate link requirements into device, interconnect, and design-rule requirements that shape future Intel process nodes.

This is a senior individual-contributor role with technical leadership across design, layout, and measurement engineers.

Responsibilities

• Define SerDes link architecture for next-generation interfaces (224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, UCIe): channel analysis, link budget, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers.
• Build and maintain system-level link models (statistical and time-domain, in MATLAB or Python; COM and IBIS-AMI based) and use them to derive block-level specifications for TX, RX, ADC, and clocking circuits.
• Lead transistor-level design of critical SerDes blocks: TX drivers (SST/CML) with FFE, RX AFE (CTLE, VGA, termination, T-coil and ESD co-design), DFE and slicers, time-interleaved ADC front ends, CDR and phase interpolators, LC and ring PLLs, and clock distribution.
• Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; correlate measured BER, eye, jitter, and power against models, and lead root-cause analysis of silicon-to-model gaps.
• Translate SerDes requirements into process and PDK requirements (device fT/fmax and parasitics, BEOL RC, inductor Q, matching, ESD capacitance budget, reliability and aging) and drive design-technology co-optimization with process, PDK, and template-library teams.
• Provide technical leadership: mentor engineers, lead design reviews, and represent Intel Foundry in technical engagements with IP partners and foundry customers.

Qualifications:

• You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelors Degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline SerDes circuit design experience -OR- Master's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 4+ years of industry experience in high-speed wireline SerDes circuit design, -OR-  Ph.D. in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 2+ years of industry experience in high-speed wireline SerDes circuit design.
• Experience in Transistor-level design of SerDes TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher.
• Experience in at least one of the following: SerDes link architecture: channel and link-budget analysis or equalization trade-off studies used to set block-level specifications.
• Lab validation of high-speed links: BER, eye, or jitter measurement and correlation to simulation.
• Behavioral or statistical link modeling in MATLAB or Python.

Preferred Qualifications

• Experience with Silicon-proven designs at 56 Gb/s PAM4 or higher, in FinFET or GAA CMOS; multiple tape-outs with block ownership.
• Experience across all three areas above (architecture, lab validation, and link modeling).
• Experience in ADC/DSP-based receivers at 112 Gb/s PAM4 or higher, including time-interleaved ADC design. - 224 Gb/s-class link development (IEEE 802.3dj, OIF CEI-224G). - PCIe Gen6/Gen7 PHY or UCIe die-to-die PHY development.
• Design experience on 5nm-class or more advanced nodes, with design-technology co-optimization experience with process teams.
• Experience in package and channel co-design: package/PCB channel modeling, signal and power integrity, crosstalk.
• Experience with first-author publications at ISSCC, VLSI Symposium, CICC, or JSSC; patents in SerDes circuits or architecture.
• Technical leadership of a multi-engineer SerDes design team through a full PHY delivery.
• Take the next step to make an impact at Intel. Join us in redefining possibilities, driving innovation, and shaping the future of technology.
• Job Type: Experienced Hire
• Shift: Shift 1 (United States of America)
• Primary Location: US, Oregon, Hillsboro
• Additional Locations: US, California, Santa Clara
• Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
• Position of Trust
• N/A