layiq
/la·yiq/adjective
worthy; deserving; fitting; suitable.
A role, opportunity, or path that merits attention, time, and pursuit.
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Open roles at NVIDIA
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Showing the newest 500 of 1,365 open roles. See all of them in Find.
- PhD Research Intern, Electronic Design Automation - 2027
US, CA, Santa Clara
- PhD Research Intern, Quantum Simulation and AI - 2027
US, CA, Santa Clara
- Senior Product Manager — Embedded AI and Next-Gen Computing
US, CA, Santa Clara
- Senior Technical Marketing Engineer, Enterprise Platform
US, CA, Santa Clara
- Research Scientist, Physical AI - Foundation Models - PhD New College Grad 2026
US, CA, Santa Clara
- Senior Applied AI Engineer, Manufacturing & System Co-Design
US, CA, Santa Clara
- Senior System and Manufacturing CoDesign Architect - Power, Thermal and Packaging
US, CA, Santa Clara; US, OR, Hillsboro
- Principal Performance and Manufacturing Architect
US, CA, Santa Clara; US, TX, Remote; US, OR, Remote; US, AZ, Remote; US, CA, Remote; US, MA, Remote
- Low-Power Feature Validation & Bring-Up Engineer
US, CA, Santa Clara
- Principal Chip Lead, Silicon Co-Design Group
US, CA, Santa Clara
- Senior Manager, System Integration – Silicon Co-Design Group
US, CA, Santa Clara
- Senior System Integration and Validation Engineer
US, CA, Santa Clara
- Senior Silicon Power, Thermal Validation and Methodology Engineer
US, CA, Santa Clara
- Senior Silicon Product Engineer, DFP – Manufacturing
US, CA, Santa Clara
- Principal Power and Thermal Architect
US, CA, Santa Clara
- Senior Manager, System Co-Design Manager - SCG Team
US, CA, Santa Clara
- Senior Silicon Circuit Co-Design Engineer
US, CA, Santa Clara
- System Verification Co-Design Engineer - Speed and Rel
US, CA, Santa Clara
- Principal System Power Management and Performance Architect
US, CA, Santa Clara; US, TX, Austin; US, OR, Hillsboro
- Senior System Integration Engineer, Memory
US, CA, Santa Clara; US, TX, Remote; US, WA, Remote; US, ID, Remote; US, CA, Remote
- HSIO Validation Lead – Silicon Co-Design
US, CA, Santa Clara
- Senior Speed Characterization Engineer - Silicon Co-Design Group
US, CA, Santa Clara
- Senior Thermal Solutions Design Engineer
US, CA, Santa Clara
- Senior System Level Testability Engineer
US, CA, Santa Clara
- Senior Power and Performance Engineer
US, CA, Santa Clara